In recent years, with the rapid development of information processing devices such as computers, high-speed and high-capacity semiconductor memory devices are being employed as key components of the information processing devices.
Typically, semiconductor memory devices may be classified into volatile semiconductor memory devices and non-volatile semiconductor memory devices. The volatile semiconductor memory devices may be further classified as dynamic random access memories and static random access memories. A volatile semiconductor memory device is fast in read and write operation but loses data when its memory cells are powered off. Non-volatile semiconductor memory devices may be further classified as a mask read only memory (MROM), a programmable read only memory (PROM), an erasable and programmable read only memory (EPROM), an electrically erasable programmable read only memory (EEPROM), and the like.
A non-volatile semiconductor memory device can permanently retain data in its memory cells even when powered off, and accordingly can be used to retain data irrespective of its power state. Once MROM, PROM, or EPROM is installed within an electronic system, it can be difficult to erase or write (program) data therein. In contrast, the EEPROM can be electrically erasable and writable more easily after installation into an electronic system using the system itself and, therefore, is increasingly being used as a system program storage unit or subsidiary storage unit which can be continuously updated.
There is a continuing demand to develop higher-density and higher-performance EEPROM devices for use in, for example, computer or microprocessor controlled electronic devices such as digital cameras and portable/notebook computers where the EEPROM may be used in place of, or to supplement, hard disk drives.
With the advance of EEPROM design and fabrication techniques, a NAND type flash EEPROM provides a flash erase function. The flash EEPROM can serve as a high-density and high-capacity subsidiary storage unit because of its higher integration than a typical EEPROM. The flash EEPROMs may be classified into a NAND type, a NOR type, and an AND type depending on the structure of the EEPROM unit memory cell array. The NAND type flash EEPROM has a higher integration than the NOR/NAND flash EEPROM, as well known in the art.
FIG. 1 is a block diagram of a conventional non-volatile semiconductor memory device, and FIG. 2 is a cross-sectional view of memory cells in the memory cell array of FIG. 1.
Referring to FIG. 1, a NAND type EEPROM memory device includes a data input/output buffer 58, a row decoder 52 for selecting word lines, a column decoder 54, a column gate 55, a sense amplifier circuit 53 for sensing and storing input/output data in memory cell transistors, a booster circuit 56 for generating a boosting voltage, a control circuit 57 for controlling operation of the memory device, and a memory cell array 51.
The memory cell array 51 includes bit lines BL 19 for transferring data to and from the memory cell transistors in a NAND cell unit (or a cell string), and word lines WL for controlling gates of the memory cell transistors and the select transistors in the NAND cell unit. The word lines WL intersect the bit lines BL 19.
Referring to FIG. 2, which shows a cross-sectional view of memory cells in the memory cell array 51 of FIG. 1, the memory cells form a NAND cell unit in a p-type well 12 formed on an n-type well 11, which is formed on a p-type substrate 10. The NAND cell unit includes a first selection transistor SST having a drain connected to the bit line 19, a second selection transistor ST having a source connected to a common source line, and 16 memory cell transistors (located under word lines WLO to WL15 and connected to the word lines WLO to WL15) having channels connected in series between a source of the first selection transistor SST and a drain of the second selection transistor ST, and which are covered by an insulation layer 18. The NAND cell unit is formed on the P-type well 12. Each memory cell transistor includes a floating gate (FG) 15 formed on the channel between source and drain regions 21 with a gate oxide layer 14 interposed between the floating gate 15 and the channel, and a control gate (CG) 17 formed over the floating gate 15 via an interlayer insulating film 16. Charges are accumulated in the floating gate 15 and function as program data by a program voltage applied to the control gate 17.
Erase, write, and read operations of the EEPROM of a NAND type will be described. The erase and write (or program) operations are conventionally performed using F-N tunneling current. For example, in the erasure operation, a very high voltage is applied to a substrate and a low voltage is applied to the CG. In this case, a floating-gate voltage Vfg is determined by a coupling ratio of a capacitance between the CG and the FG and a capacitance between the FG and the substrate, and is applied to the FG. When a voltage difference between the floating-gate voltage Vfg applied to the FG and the substrate voltage Vsub applied to the substrate is greater than a voltage difference for F-N tunneling, the electrons accumulated in the FG move to the substrate. The electron movement decreases a threshold voltage Vt of the memory cell transistor having the CG, the FG, the source and the drain. When a sufficiently high voltage is applied to the drain, current flows, because the Vt sufficiently decreases, even though 0V is applied to the CG and the source. This state is considered to be “erased” and commonly indicated as logic “1”.
In contrast, in the write operation, 0V is applied to the source and the drain and a very high voltage is applied to the CG. In this case, an inversion layer is formed in the channel and both the source and the drain will have a potential of 0V. If a voltage difference between the floating-gate voltage Vfg, determined by a coupling ratio of a capacitance between the CG and the FG and a capacitance between the FG and the substrate, and the channel voltage Vchannel (0V) is enough to cause F−N tunneling, the electrons move from the channel region to the FG. The electron movement increases the threshold voltage Vt. Even though a predetermined voltage is applied to the CG, 0V is applied to the source and a proper voltage is applied to the drain, the current does not flow. This state is considered to be “programmed” and commonly indicated as logic “0”.
In the structure of the memory cell array, a unit page refers to memory cell transistors having control gates connected to one word line in common. Each of a plurality of pages including a plurality of memory cell transistors is called a cell block. A unit cell block commonly includes one or more cell strings per bit line. The NAND flash memory has a page program mode for fast programming. Page program operation includes data loading operation and program operation. In the data loading operation, data in bytes from input/output terminals are sequentially latched and stored in data registers. The data registers correspond to the bit lines, respectively. In the program operation, the data in the data registers are simultaneously written to memory cell transistors on the selected word line via the bit lines.
As described above, in the NAND type EEPROM, the read, program, and write operations are generally performed in units of page while the erasure operation is performed in units of block. In fact, the electron movement between the FG and the channel of the memory cell transistor occurs only in the program and erasure operations. In the read operation, data is read from memory cell transistors without the risk of causing data loss after the erase and program operations are terminated.
In the read operation, a higher voltage (typically, a read voltage) than a voltage (typically, a ground voltage) applied to the CG of the selected memory cell transistor is applied to the CG of an unselected memory cell transistor. Accordingly, current flows or does not flow on a corresponding bit line depending on a program state of the selected memory cell transistor. If a threshold voltage of the programmed memory cell is higher than a reference value in a determined voltage condition, the memory cell is detected as an off-cell and a high voltage is charged on a relevant bit line. In contrast, if the threshold voltage of the programmed memory cell is lower than the reference value, the memory cell is detected as an on-cell, and a relevant bit line is discharged to a low level. This bit line state is finally detected as “0” or “1” by a sense amplifier (53 of FIG. 1) called a page buffer.
In a memory cell area of the flash EEPROM, an area on which the read operation is mainly performed may be an area storing a few code data, such as ROM table information or indexing information to data in a main memory cell array, which needs to be fast accessed. Read disturbance caused by read operation occurs in memory cells belonging to such an area. That is, after code data is read from the memory cells over threshold times, reading data fails due to read voltage stress applied each time the memory cells are not selected, resulting in a read error.
Consequently, as the read operation is repetitively performed more than a threshold number of times on a specific memory cell area, the threshold voltage of memory cells may vary, resulting in a read error. In this case, it is difficult to correct data having a read error using, for example, an error correction code, and which results in an entire memory device defect.
Accordingly, there is a need for a solution for preventing, in advance, a read error due to read disturbance in a non-volatile semiconductor memory.